In a typical data bus communications system, data and address signals are placed on the data bus by the bus controller, or bus master. Thereafter a control signal indicating readiness for a data transfer is signalled to the peripheral (slave unit) device. The peripheral device may either acknowledge the transfer by an acknowledge return signal, or otherwise indicate a busy condition by a return control signal, if unable to complete the data transfer.
The control signal between master and slave units can be either an absolute logic level, or a transition signal, as is known in the prior art. Absolute logic level signalling means that a given logic level, say a logic 1, indicates a readiness to transfer data. In general, in transition signalling, the indication of readiness is the signal transition, i.e. the transition from one logic level to another, rather than the absolute logic level.
Transition signalling, as compared to logic level signalling, speeds up a data bus because twice as many operations can occur in a given time interval. That is, for a maximum signal rate of 30 Mhz for example, a maximum transfer of 30 Mhz is possible using logic level signal indication. The same limitation arises if only one edge of the control signals, i.e. the rising edge or the falling edge, is utilized. However, by using transition signalling, data can be transferred on both the rising and falling transitions of the control signals. Therefore, using transition signalling, a maximum data transfer rate of 60 Mhz is possible.
The usual way of using transition signalling for a communication channel is the two-phase interface. In a standard two-phase interface, there are two control wires and a number of data wires. The control wires are called REQ and ACK, for request and acknowledge, respectively. The REQ signal is controlled by the sender, and the ACK by the receiver. As the name suggests, the state of the communication channel is in one of two phases.
In the first phase, the REQ signal is allowed to transition, but the ACK is not. This is the "idle" phase.
In practice, the channel remains in the first phase until the sender is ready to send a word of data, at which point it places the word on the data wires and transitions REQ. This causes the channel to enter the second phase.
In the second phase, the REQ signal is not allowed to transition, but the ACK is. During this phase, one word of data is presented on the data lines.
In practice, the channel will remain in the second phase until the receiver is ready to accept the word, at which point it will transition ACK, and the channel reverts to the first phase.
The two-phase interface is very straightforward when there is communication when there is only one sender and one receiver. The present invention is an enhanced version that is usable on a bus with more than two devices.
The two-phase interface makes it straightforward to use transition signalling on a bus with only one master and one slave communicating.
However, on a bus serving three or more devices, i.e. one master unit and more than one slave device, transition signalling is considerably more difficult. In order for three or more devices to share a single control line, the logic is either tri-state or open collector. If a previous data transfer leaves a control signal in logic low condition it is difficult for another peripheral device to transition signal on that control line and force to a high condition. It is not impossible, and one way is use a capacitor on the control line. However, use of a capacitor has two problems. First, high load capacitance on the control line slows down operation considerably. Second, the circuit would be dynamic and not work down to 0 Hz, probably causing software problems.